`timescale 1ns/1ns
module tx_test;
  reg clk,rst,Rx_en,bps_clk;
  reg [7:0] tx_data;
  wire Tx_pin_out;
  wire idle_sig,end_sig;
  tx u1(clk,rst,Rx_en,tx_data,bps_clk,Tx_pin_out,idle_sig,end_sig);
  initial
  begin
    clk=0;rst=0;Rx_en=1;bps_clk=0;tx_data=0;
    #10 rst=1;
    #10 Rx_en=0; bps_clk=1;tx_data[7:0]=8'b11001110;
    #10 
    #120 $stop;
  end
  always #5 clk=~clk;
  initial $monitor($time, , ,"clk=%b rst=%b Tx_en=%b tx_data=%b bps_clk=%b Tx_pin_out=%b",clk,rst,Rx_en,tx_data,bps_clk,Tx_pin_out);
endmodule